1. Technical Field
The present invention relates to a test apparatus and test method. Particularly, the present invention relates to a test apparatus and test method suitable for testing a large number of relatively small-size semiconductor devices.
2. Description of the Related Art
Japanese Patent Application Publication No. 2005-249735 discloses a pattern generator and a testing apparatus which are capable of efficiently generating a continuous test pattern used for testing an electronic device. The pattern generator disclosed in the above publication first stores test data blocks onto a cache memory in an order designated by designation information, and then sequentially outputs the test data blocks stored on the cache memory as a test pattern. According to the above publication, a single controller controls a plurality of pattern generators, and the pattern generators under the control of the controller test a single independent electronic device. This means that the pattern generators controlled by the single controller receive a single piece of designation information and that each pattern generator may not be capable of generating a test pattern independently.
When the pattern generators configured in the above manner are utilized to test a relatively small-size electronic device, that is to say, an electronic device with a small number of test target terminals, the number of the pattern generators controlled by the single controller may sometimes be larger than the number of the test target terminals. In other words, one or more redundant pattern generators may not be connected to the test target terminals to be tested and thus not used, which may in turn lower the overall testing efficiency of the testing apparatus.